Clock module

The clock module can generate a clock synthetized from the FPGA system clock, using a 8-bits clock divisor. The frequency can be changed during a short amount of time by switching to a secondary clock divisor in order to generate clock glitches.

Warning

This module is still experimental and may be subject to changes.

Python API example

clock = scaffold.clock0
clock.frequency = 1e6
clock.glitch_frequency = 4e6
clock.glitch_count = 20  # Number of glitching clock edges
clock.out >> scaffold.d0
clock.glitch << scaffold.d1  # Glitch trigger

For more API documentation, see scaffold.Clock

Signals

Internal registers

clock0

0x0a00

base + 0x0000	config	W
base + 0x0001	divisor_a	W
base + 0x0002	divisor_b	W
base + 0x0003	count	W

config register

7	6	5	4	3	2	1	0
reserved

divisor_a register

This 8-bits register can be configured to adjust the primary clock frequency. Effective frequency is

Effective clock frequency is:

\[F = \frac{F_{sys}}{(D+1)*2}\]

Where \(F_{sys}\) is the system frequency and \(D\) the divisor value. The value of \(D\) for a target frequency \(F\) is:

\[D = \frac{ F_{sys} }{ 2*F } - 1\]

The highest possible frequencies are 50 MHz, 25 MHz, 16.66 MHz, 12.5 MHz… The lowest possible frequency is 196.08 kHz.

divisor_b register

This 8-bits register can be configured to adjust the secondary clock frequency. Frequency calculation is the same as divisor_a register.

count register

This 8-bits register configures the number \(N\) of glitched clock edges, where \(N\) is the register value plus one.